stP80NF55l-06 n - channel 55v - 0.005 w - 80a to-220 stripfet ? power mosfet n typical r ds(on) = 0.005 w n low threshold drive n logic level device description this power mosfet is the latest development of stmicroelectronics unique osingle feature size ? o strip-based process. the resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. applications n high current, high speed switching n solenoid and relay drivers n motor control, audio amplifiers n dc-dc & dc-ac converters ? internal schematic diagram october 1999 absolute maximum ratings symbol parameter value unit v ds drain-source voltage (v gs =0) 55 v v dgr drain- gate voltage (r gs =20k w )55v v gs gate-source voltage 20 v i d drain current (continuous) at t c =25 o c80a i d drain current (continuous) at t c = 100 o c57a i dm ( ? ) drain current (pulsed) 320 a p tot total dissipation at t c =25 o c 210 w derating factor 1.4 w/ o c e as ( 1 ) single pulse avalanche energy 1 j t stg storage temperature -65 to 175 o c t j max. operating junction temperature 175 o c ( ? ) pulse width limited by safe operating area ( 1 ) starting t j =25 o c, i d =40a , v dd = 30v type v dss r ds(on) i d stP80NF55l-06 55 v < 0.0065 w 80 a 1 2 3 to-220 1/8
thermal data r thj-case r thj-amb t l thermal resistance junction-case max thermal resistance junction-ambient max maximum lead temperature for soldering purpose 0.71 62.5 300 o c/w o c/w o c electrical characteristics (t case =25 o c unless otherwise specified) off symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d =250 m av gs =0 55 v i dss zero gate voltage drain current (v gs =0) v ds =maxrating v ds =maxrating t c =125 o c 1 10 m a m a i gss gate-body leakage current (v ds =0) v gs = 20 v 100 na on ( * ) symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds =v gs i d = 250 m a11.62.5v r ds(on) static drain-source on resistance v gs =10v i d =40a v gs =5v i d =40a 0.005 0.0055 0.0065 0.008 w w i d(o n) on state drain current v ds >i d(o n) xr ds(on )ma x v gs =10v 80 a dynamic symbol parameter test conditions min. typ. max. unit g fs ( * )forward transconductance v ds >i d(o n) xr ds(on )ma x i d =18 a 20 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds =25v f=1mhz v gs = 0 7600 990 270 pf pf pf stP80NF55l-06 2/8
electrical characteristics (continued) switching on symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v dd =27v i d =40a r g =4.7 w v gs =4.5v (resistive load, see fig. 3) 75 300 ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd =44v i d =80a v gs =5v 97 25 46 100 nc nc nc switching off symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off delay time fall time v dd =27v i d =40a r g =4.7 w v gs =4.5v (resistive load, see fig. 3) 210 160 ns ns t d(off) t f t c off-voltage rise time fall time cross-over time vclamp = 44 v i d =80a r g =4.7 w v gs =4.5v (inductive load, see fig. 5) 90 230 350 ns ns ns source drain diode symbol parameter test conditions min. typ. max. unit i sd i sdm ( ? ) source-drain current source-drain current (pulsed) 80 320 a a v sd ( * )forwardonvoltage i sd =80a v gs =0 1.5 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 80 a di/dt = 100 a/ m s v dd =25v t j =150 o c (see test circuit, fig. 5) 75 190 5.1 ns nc a ( * ) pulsed: pulse duration = 300 m s, duty cycle 1.5 % ( ? ) pulse width limited by safe operating area safe operating area thermal impedance stP80NF55l-06 3/8
output characteristics transconductance gate charge vs gate-source voltage transfer characteristics static drain-source on resistance capacitance variations stP80NF55l-06 4/8
normalized gate threshold voltage vs temperature source-drain diode forward characteristics normalized on resistance vs temperature stP80NF55l-06 5/8
fig. 1: unclamped inductive load test circuit fig. 3: switching times test circuits for resistive load fig. 2: unclamped inductive waveform fig. 4: gate charge test circuit fig. 5: test circuit for inductive load switching and diode recovery times stP80NF55l-06 6/8
dim. mm inch min. typ. max. min. typ. max. a 4.40 4.60 0.173 0.181 c 1.23 1.32 0.048 0.051 d 2.40 2.72 0.094 0.107 d1 1.27 0.050 e 0.49 0.70 0.019 0.027 f 0.61 0.88 0.024 0.034 f1 1.14 1.70 0.044 0.067 f2 1.14 1.70 0.044 0.067 g 4.95 5.15 0.194 0.203 g1 2.4 2.7 0.094 0.106 h2 10.0 10.40 0.393 0.409 l2 16.4 0.645 l4 13.0 14.0 0.511 0.551 l5 2.65 2.95 0.104 0.116 l6 15.25 15.75 0.600 0.620 l7 6.2 6.6 0.244 0.260 l9 3.5 3.93 0.137 0.154 dia. 3.75 3.85 0.147 0.151 l6 a c d e d1 f g l7 l2 dia. f1 l5 l4 h2 l9 f2 g1 to-220 mechanical data p011c stP80NF55l-06 7/8
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibil ity for the consequences of use of such information nor for any infringement of patents or other rights of third part ies which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectro nics. specific ation mentioned in this publication are subjec t to change without notice. this publication supersedes and replaces all informat ion previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems with out express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics ? 1999 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com . stP80NF55l-06 8/8
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